This invention relates to a method for manufacturing a gate array integrated circuit device which comprises a logic system provided on a semiconductor substrate, and moreover relates to a new concept for an expanded macro cell which comprises plural macro cells.
In gate array technology, a manufacturer prepares a master bulk pattern which includes basic cells in array form on a semiconductor substrate, prior to the submission of detailed design data for a particular logic system. After finishing the design of the logic system, the customer, i.e. system designer, supplies detailed design data, describing the particular logic system, to the manufacturer. Thereafter, the manufacturer produces a wiring pattern according to this logic system information and provides the wiring pattern on the semiconductor substrate which connects the basic cells. Unlike the fully customized integrated circuit device technology, in which the manufacturer must develop not only a wiring pattern but also a custom bulk pattern on a semiconductor substrate, the "semi-custom" gate array technology has advantages in that the turn-around time on a design is very short, because the manufacturer only has to produce a wiring pattern. Moreover, although the manufacturing cost is lower than that of a full-custom integrated circuit device, the system designer still receives the originally designed integrated circuit device.
Recently, the complexity and density of gate array integrated circuit devices has become greater, in part due to the fact that the logic systems designed by customers have become more complex. In conventional gate array design technology, when a system designer creates a new original logic system, he usually makes up a logic diagram for the logic system by using symbols for macro cells, each of which comprises a basic cell or a group of several basic cells. Therefore, if the logic system is very complex, even if the logic diagram of the logic system is drawn in symbols representing the macro cells, this type of logic diagram is still complex for designers. This makes it very difficult to understand the system logic from the logic diagram; and also makes it very difficult for logic system designers to design an accurate logic diagram based on their original idea, thereby resulting in a significant number of errors and increasing the design cycle time.